This invention relates to microelectronic packaging devices and methods, and more particularly relates to solder bumps for microelectronic substrates and methods of fabricating and testing same.
As electronic devices continue to be miniaturized, the mounting of a microelectronic substrate to another microelectronic substrate may become increasingly difficult. Thus, high density, high performance and reliable interconnection techniques are desirable for microelectronic substrates. It will be understood by those having skill in the art that microelectronic substrates include but are not limited to integrated circuit chips, wafers, printed circuit boards, multi-chip module substrates, ceramic substrates, glass substrates and any other electronic packaging substrates that are used in microelectronic systems including optoelectronic systems.
In order to satisfy these requirements, solder bump technology is increasingly being used for microelectronic packaging. Solder bump technology is also referred to as C4 (controlled collapse circuit connection) or xe2x80x9cflip chipxe2x80x9d technology. Solder bump technology can allow a bare integrated circuit to be mounted on a next level package, without requiring encapsulation of the integrated circuit. Moreover, solder bump technology can utilize the entire area of a microelectronic substrate for connection rather than only using the periphery thereof. High performance may be obtained because high frequency signal transmission may be obtained due to direct bonding.
Conventional solder bumps generally use an alloy of lead (Pb) and another metal. Specifically, an alloy of 95% lead and 5% tin (Sn) is widely used. Unfortunately, the use of the lead may be harmful for the environment, so that alternatives to lead are being investigated. Alloys of silver (Ag) and tin (Sn) have been investigated as alternatives to lead-based alloys for solder bumps. However, since solder bumps are generally plated on an underbump metallurgy using a mask, it may be difficult to plate silver-tin alloy solder bumps as opposed to lead-tin solder bumps. Although it may be possible to use paste screening processes to form silver-tin alloy solder bumps, plating may be preferred for high-density solder bump interconnections.
It is therefore an object of the present invention to provide improved solder bump structures for microelectronic substrates and methods of fabricating and testing same.
It is another object of the present invention to provide improved silver-tin alloy solder bumps and methods of fabricating and testing same.
These and other objects are provided, according to the present invention, by forming a masked underbump metallurgy layer on a microelectronic substrate, to define exposed portions of the underbump metallurgy layer, plating silver on the exposed portions of the underbump metallurgy, plating tin on the silver and reflowing to form silver-tin alloy solder bumps. Accordingly, silver-tin alloy is not plated. Rather, individual layers of silver and tin are plated, and then reflowed to form silver-tin alloy solder bumps.
The masked underbump metallurgy layer is preferably formed by forming a continuous underbump metallurgy layer on the microelectronic substrate and forming a patterned mask layer on the continuous underbump metallurgy layer, to define the exposed portions of the underbump metallurgy layer. The patterned mask layer is preferably removed after the tin is plated and before reflowing. Moreover, the portions of the continuous underbump metallurgy layer that are not between the microelectronic substrate and the tin are also preferably removed prior to reflowing, so that reflowing can result in formation of solder bumps. In order to aid in reflowing, the silver and tin layers may be coated with flux prior to reflowing and the flux may be removed after reflowing.
When plating the tin on the silver using a mask, tin may be plated on the silver and extend onto the mask opposite the underbump metallurgy to form a mushroom shape. After removing the mask, reflowing is performed by heating at temperature and time that are sufficient to melt the tin and to diffuse at least some of the silver into the tin.
The masked underbump metallurgy layer preferably comprises a first underbump metallurgy layer on the microelectronic substrate that is selected from the group consisting of titanium (Ti), chromium (Cr) and titanium tungsten (TiW). A second underbump metallurgy layer is formed on the first underbump metallurgy layer opposite the microelectronic substrate. The second underbump metallurgy layer is preferably selected from the group consisting of copper (Cu) and nickel (Ni).
The steps of plating silver and plating tin are preferably performed by electroplating silver and electroplating tin. Silver may be electroplated at temperature between 15xc2x0 C. and 30xc2x0 C., at current density between 10 mA/cm2 and 14 mA/cm2 and time between 13 minutes and 17 minutes. Tin may be electroplated at temperature between 15xc2x0 C. and 30xc2x0 C., at current density between 18 mA/cm2 and 22 mA/cm2 and time between 35 minutes and 45 minutes. These parameters can electroplate a silver thickness between 9 xcexcm and 11 xcexcm and a tin thickness between 38 xcexcm and 42 xcexcm. Reflowing may be performed by heating at temperatures between 240xc2x0 C. and 330xc2x0 C. The reflow may produce silver-tin alloy solder bumps that are between 2.5% and 4.5% silver and 97.5% and 95.5% tin.
In order to test the silver-tin alloy solder bumps, silver-tin alloy solder bumps may be fabricated as described above, and then sectioned. The sectioned silver-tin alloy solder bumps are then analyzed. The solder bumps may be sectioned by mounting the sectioned solder bumps in an epoxy resin, polishing the solder bumps and etching the mounted solder bumps. They may then be analyzed by performing electron probe microanalysis on the sectioned silver-tin alloy solder bumps and/or performing scanning electron microscopy on the sectioned silver-tin alloy solder bumps.
In another testing method, first and second silver layers are plated, having corresponding first and second thicknesses, on the underbump metallurgy. Tin is then plated on the first and second silver layers. Reflowing is then performed to form first and second solder bumps of differing silver-tin alloy compositions. First and second solder bumps are then analyzed. Multiple reflowing and analyzing steps may be performed in sequence in order to analyze the composition and other parameters of the solder bumps during different reflow times.
Solder bump structures for microelectronic substrates according to the invention include an underbump metallurgy layer on the microelectronic substrate, a first layer comprising silver on the underbump metallurgy layer opposite the microelectronic substrate and a second layer comprising tin on the first layer opposite the underbump metallurgy layer. The second layer comprising tin is preferably a second layer comprising silver-tin alloy.
During intermediate fabrication, the second layer may be a mushroom-shaped second layer comprising tin. In the final solder bump structure, the second layer is preferably a truncated spherical-shaped second layer comprising tin, and preferably comprising silver-tin alloy. A flux coating may be included during intermediate fabrication. The underbump metallurgy may be a two-layer structure as already described, and the thicknesses and compositions of the first and second layers and the silver-tin alloy may be as already described. Accordingly, high performance solder bump structures and fabrication and testing methods may be provided, that need not be detrimental to the environment.